1. Field of the Invention
The present invention relates to a semiconductor package and, more particularly, to a structure and a fabricating method of a semiconductor package, which is simple in the fabricating process and suitable for improving a reliability of a device.
2. Discussion of the Related Art
In fabrication of a semiconductor package, in general, successive steps of a process are conducted, including dicing for separating chips or integrated circuits fabricated on a wafer, chip bonding for setting the separated chips on paddles in a lead frame, wire bonding for electrically connecting bonding pads on the chips and inner leads of the lead frame, and molding the circuit for protection.
A conventional semiconductor package will be explained with reference to the attached drawing. FIG. 1 illustrates a sectional structure of a conventional wire bonding semiconductor package.
Referring to FIG. 1, the conventional semiconductor package includes a chip 11 with a built-in semiconductor circuit, a lead frame 12 connected to and for supporting the chip 11, a double-sided adhesive tape 13 for fixing the chip 11 and the lead frame 12, lower pads 15 formed below the lead frame 12 for connecting a PCB (Printed Circuit Board) 14 and the lead frame 12, bonding pads 16 formed on upper portions of the chip 11 for acting as electrodes, wires 17 for electrically connecting electrical connection of the boding pads 16 to the lead frame 12, and a body 18 of EMC(Epoxy Mold Compound) for protecting the device from external environment.
The aforementioned conventional semiconductor package has the following problems.
First, the wire boding process for electrical connection of the chip to the lead frame causes the fabrication process to be complicated and requires a complicated soldering process following the step of stacking the chips.
Second, no heat sinks are provided for dissipation of heat generated during the device operation such the electrical shorts or heating of the semiconductor device may occur.
Third, the conventional semiconductor package is configured such that the packages stacked up on top of each other do not appear very attractive and stable.